@Article{app11146490,
AUTHOR = {Saralegui, Roberto and Sanchez, Alberto and de Castro, Angel},
TITLE = {Modeling of Deadtime Events in Power Converters with HalfBridge Modules for a Highly Accurate HardwareintheLoop Fixed Point Implementation in FPGA},
JOURNAL = {Applied Sciences},
VOLUME = {11},
YEAR = {2021},
NUMBER = {14},
ARTICLENUMBER = {6490},
URL = {https://www.mdpi.com/20763417/11/14/6490},
ISSN = {20763417},
ABSTRACT = {Hardwareintheloop (HIL) simulations of power converters must achieve a truthful representation in real time with simulation steps on the order of microseconds or tens of nanoseconds. The numerical solution for the differential equations that model the state of the converter can be calculated using the fourthorder Runge–Kutta method, which is notably more accurate than Euler methods. However, when the mathematical error due to the solver is drastically reduced, other sources of error arise. In the case of converters that use deadtimes to control the switches, such as any power converter including halfbridge modules, the inductor current reaching zero during deadtimes generates a model error large enough to offset the advantages of the Runge–Kutta method. A specific model is needed for such events. In this paper, an approximation is proposed, where the time step is divided into two semisteps. This serves to recover the accuracy of the calculations at the expense of needing a division operation. A fixedpoint implementation in VHDL is proposed, reusing a block along several calculation cycles to compute the needed parameters for the Runge–Kutta method. The implementation in a lowcost fieldprogrammable gate arrays (FPGA) (Xilinx Artix7) achieves an integration time of 1µs. The calculation errors are six orders of magnitude smaller for both capacitor voltage and inductor current for the worst case, the one where the current reaches zero during the deadtimes in 78% of the simulated cycles. The accuracy achieved with the proposed fixed point implementation is very close to that of 64bit floating point and can operate in real time with a resolution of 1µs. Therefore, the results show that this approach is suitable for modeling converters based on halfbridge modules by using FPGAs. This solution is intended for easy integration into any HIL system, including commercial HIL systems, showing that its application even with relatively high integration steps (1µs) surpasses the results of techniques with even faster integration steps that do not take these events into account.},
DOI = {10.3390/app11146490}
}
