@Article{electronics8101116, AUTHOR = {Yushkova, Marina and Sanchez, Alberto and de Castro, Angel and Martínez-García, M. Sofía}, TITLE = {A Comparison of Filtering Approaches Using Low-Speed DACs for Hardware-in-the-Loop Implemented in FPGAs}, JOURNAL = {Electronics}, VOLUME = {8}, YEAR = {2019}, NUMBER = {10}, ARTICLE-NUMBER = {1116}, URL = {https://www.mdpi.com/2079-9292/8/10/1116}, ISSN = {2079-9292}, ABSTRACT = {The use of Hardware-in-the-Loop (HIL) systems implemented in Field Programmable Gate Arrays (FPGAs) is constantly increasing because of its advantages compared to traditional simulation techniques. This increase in usage has caused new challenges related to the improvement of their performance and features like the number of output channels, while the price of HIL systems is diminishing. At present, the use of low-speed Digital-to-Analog Converters (DACs) is starting to be a commercial possibility because of two reasons. One is their lower price and the other is their lower pin count, which determines the number and price of the FPGAs that are necessary to handle those DACs. This paper compares four filtering approaches for providing suitable data to low-speed DACs, which help to filter high-speed input signals, discarding the need of using expensive high-speed DACS, and therefore decreasing the total cost of HIL implementations. Results show that the selection of the appropriate filter should be based on the type of the input waveform and the relative importance of the dynamics versus the area.}, DOI = {10.3390/electronics8101116} }