@Article{electronics9010081, AUTHOR = {Sanchez, Alberto and de Castro, Angel and Martínez-García, Maria Sofía and Garrido, Javier}, TITLE = {LOCOFloat: A Low-Cost Floating-Point Format for FPGAs.: Application to HIL Simulators}, JOURNAL = {Electronics}, VOLUME = {9}, YEAR = {2020}, NUMBER = {1}, ARTICLE-NUMBER = {81}, URL = {https://www.mdpi.com/2079-9292/9/1/81}, ISSN = {2079-9292}, ABSTRACT = {One of the main decisions when making a digital design is which arithmetic is going to be used. The arithmetic determines the hardware resources needed and the latency of every operation. This is especially important in real-time applications like HIL (Hardware-in-the-loop), where a real-time simulation of a plant—power converter, mechanical system, or any other complex system—is accomplished. While a fixed-point gets optimal implementations, using considerably fewer resources and allowing smaller simulation steps, its use is very restricted to very specific applications, as its design effort is quite high. On the other side, IEEE-754 floating-point may have resolution problems in case of the 32-bit version, and excessive hardware usage in case of the 64-bit version. This paper presents LOCOFloat, a low-cost floating-point format designed for FPGA applications. Its key features are soft normalization of the results, using significand and exponent fields in two’s complement. This paper shows the implementation of addition, subtraction and multiplication of the proposed format. Both IEEE-754 versions and LOCOFloat are compared in this paper, implementing a HIL model of a buck converter. Although the application example is a HIL simulator, other applications could take benefit from the proposed format. Results show that LOCOFloat is as accurate as 64-bit floating-point, while reducing the use of DSPs blocks by 84 % .}, DOI = {10.3390/electronics9010081} }